MI450 WMMA and ds_load Scheduling via a DAG Mutation

The following talk was given at the end of my internship at AMD. A pain point many GPU kernel developers deal with is the very complex instruction schedulers in LLVM failing to make certain critical decisions that ultimately decide whether a kernel is sufficiently fast. Such decisions are (but not limited to): scheduling load instructions further away from its first consumer then the load's latency (so it's ready in time), scheduling loads alongside matrix multiplication instructions so their latency is hidden, scheduling load instructions sufficiently away from each other to prevent overwhelming the LDS bus, and scheduling loads sufficiently close to their consumers so that a register isn't occupied but unused.

Failure to successfully make these decisions can lead to absolutely terrible slowdowns due to spills from high register pressure and stalls waiting on loads to finish. The following presentation goes over my solution to address these problems for AMD's CoExecScheduler in LLVM.

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